System-on-a-Chip Verification - Methodology and Techniques

Book Description

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application. System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter: Explanation of the objective involved in performing verification after a given design step; Features of options available; When to use a particular option; How to select an option; and Limitations of the option. This exciting new book will be of interest to all designers and test professionals.

Customer Reviews:

DIGITAL System on a Chip, Not ANALOG.......2003-02-28

This may be the world's most complete over view of digital system-on-a-chip verification. I don't know.

I was excited to find a book on this subject, because this is a specialized subject not covered well by the publishing industry, because this is a subject that is very difficult to write about, with only perhaps a few tens of thousands of active specialists, and because of these quotations from the book's back cover "[fully covers] system on a chip," "Bluetooth because it addresses reality," "comprehensive guide to overall SOC verification," "authors... leave no stone unturned in this comprehensive overview of [chip verification] tools and methodolgies."

Now that I have received the book, I feel that it is important to make note of what I know this book is not. It is not a book with any significant coverage of analog.

I am an analog chip designer that has 24 years experience, a good part of that time spent verifying my analog and mixed-signal designs. This book has a single 24 page chapter on analog, "Analog/Mixed-Signal Simulation," which taught me nothing. The chapter lists and defines the standard specialized nomenclature of the analog verification software, gives an example simple VerilogA behavioral model for a crude resistor-transresistor DAC, and gives a crude behavioral test example. I think that most all stones are left unturned for analog or mixed-signal chip verification. The authors mention SPICE, spectre, and Cadence Analog Design Environment only. I just finished a 37000 transistor analog & mixed-signal chip verification, and this book mentioned none of the tools and methods that I used, which included Mentor's Modeltech Modelsim and Synopsys's Saber. The examples are of value in giving existing digital chip verification experts an example of how to get started with a crude VerilogA behavioural modeling of analog blocks to be fit into a digital chip verification flow.

All of the authors are or were associated with Cadence Design Systems, according to the book. They write "The [EDA software] industry has been slow in responding to the mixed-signal design and simulation requirements." "Analog engineers have been using [SPICE] for analog simulation for over 30 years..." "The third VSIA verification meeting concluded 'verification is not just very hard, it is very, very hard.'" I agree, but there is still much left to write about. I congratulate them on being some of the first to attempt such a writing task.

Poor examples explanation.......2002-11-09

I am not an expert in this field but what I learn are just some simple concepts. It takes some pages on the bluetooth SOC design
example with fractional C code. There is no structure about the examples and its hard to understand what the authors will explain(actually, I just feel ??what??)

Retargetable Compilers for Embedded Core Processors: Methods and Experiences in Industrial Applications

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Retargetable Compilers for Embedded Core Processors: Methods and Experiences in Industrial Applications
Clifford Liem
Manufacturer: Springer
ProductGroup: Book
Binding: Hardcover

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ASIN: 0792399595

Book Description

Embedded core processors are becoming a vital part of today's system-on-a-chip in the growing areas of telecommunications, multimedia and consumer electronics. This is mainly in response to a need to track evolving standards with the flexibility of embedded software. Consequently, maintaining the high product performance and low product cost requires a careful design of the processor tuned to the application domain. With the increased presence of instruction-set processors, retargetable software compilation techniques are critical, not only for improving engineering productivity, but to allow designers to explore the architectural possibilities for the application domain.
Retargetable Compilers for Embedded Core Processors, with a Foreword written by Ahmed Jerraya and Pierre Paulin, overviews the techniques of modern retargetable compilers and shows the application of practical techniques to embedded instruction-set processors. The methods are highlighted with examples from industry processors used in products for multimedia, telecommunications, and consumer electronics. An emphasis is given to the methodology and experience gained in applying two different retargetable compiler approaches in industrial settings. The book also discusses many pragmatic areas such as language support, source code abstraction levels, validation strategies, and source-level debugging. In addition, new compiler techniques are described which support address generation for DSP architecture trends. The contribution is an address calculation transformation based on an architectural model.
Retargetable Compilers for Embedded Core Processors will be of interest to embedded system designers and programmers, the developers of electronic design automation (EDA) tools for embedded systems, and researchers in hardware/software co-design.

Internet Applications in LabVIEW (With CD-ROM)

Average customer rating:

Wonderful intro to networking
An Excellent and Compact source of information
A Must have for Network and Internet LabVIEW Coders
I needed to control my labview vis over the web
Clears up many questions about Internet technology

Internet Applications in LabVIEW (With CD-ROM)
Jeffrey Travis
Manufacturer: Prentice Hall PTR
ProductGroup: Book
Binding: Paperback

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ASIN: 0130141445

Customer Reviews:

Wonderful intro to networking.......2001-05-07

This book provided me with much more knowledge than I expected when I bought it. It covers networking and internet basics and explains technologies such as TCP, IP, and UDP for a beginner a well as the various networking tools provided by LabVIEW in detail. It is a perfect mix of background and general info with LabVIEW detail. This is definitely a great book to get into networked apps with.

An Excellent and Compact source of information.......2000-08-10

With 10+ years of LabVIEW programming experience I found Jeff's book to be an excellent and compact source of internet and network applications in LabVIEW. The background was excellent and not overly in depth. The sample programs on the CD consumed hours of my time examining all the great examples it contained. My copy is littered with underlines, highlights and post-it notes marking the good spots! (he should have simply printed the pages in yellow paper!)

For LabVIEW programmers it's an excellent timesaver for internet info and apps in LabVIEW.

A Must have for Network and Internet LabVIEW Coders.......2000-08-10

With 10+ years programming in LabVIEW this book was very useful and on the mark with explaining internet technologies. Well worth the money in time you'd spend looking for this info all over the net.

I needed to control my labview vis over the web.......2000-08-04

this book is dense and packed with more information than you probably will use, but i gave it five stars because it does have everything you need, theory and examples, for controlling your vis over the web. you learn to use java and activex, step-by-step.

with the software and examples in this book, i was able to set up a web browser control of my chemistry lab.

Clears up many questions about Internet technology.......2000-08-04

This book filled in the gap for me on many questions I had about Web servers, security, Web pages, etc. Great resource.

Average customer rating:

Switching Theory for Logic Synthesis
Tsutomu Sasao
Manufacturer: Springer
ProductGroup: Book
Binding: Hardcover

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ASIN: 0792384563

Book Description

Switching Theory for Logic Synthesis covers the basic topics of switching theory and logic synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation. Chapters 6 through 8 include an introduction to sequential circuits, optimization of sequential machines and asynchronous sequential circuits. Chapters 9 through 14 are the main feature of the book. These chapters introduce and explain various topics that make up the subject of logic synthesis: multi-valued input two-valued output function, logic design for PLDs/FPGAs, EXOR-based design, and complexity theories of logic networks.
An appendix providing a history of switching theory is included. The reference list consists of over four hundred entries.
Switching Theory for Logic Synthesis is based on the author's lectures at Kyushu Institute of Technology as well as seminars for CAD engineers from various Japanese technology companies.
Switching Theory for Logic Synthesis will be of interest to CAD professionals and students at the advanced level. It is also useful as a textbook, as each chapter contains examples, illustrations, and exercises.

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APPLICATION OF COMPUTERS IN TECHNOLOGY
Emilio Laca
Manufacturer: Kendall-Hunt
ProductGroup: Book
Binding: Spiral-bound

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ASIN: 0757515711

Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler and Primetime

Average customer rating:

Practical Text
very general; very short; and way over priced
very general; very short; not worth the money
Advanced Asic Chip Synthesis: Using Synopsys Design Compiler
Highly overpriced, bad English, poor typeset

Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler and Primetime
Himanshu Bhatnagar
Manufacturer: Springer
ProductGroup: Book
Binding: Hardcover

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ASIN: 0792385373

Book Description

Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® and PrimeTime® describes the advanced concepts and techniques used for ASIC chip synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.
The emphasis of this book is on real-time application of Synopsys tools used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-arounds described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solutions.
Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® and PrimeTime® is intended for anyone who is involved in the ASIC design methodology, starting from RTL synthesis to final tape-out. Target audiences for this book are practicing ASIC design engineers and graduate students undertaking advanced courses in ASIC chip design and DFT techniques.
From the Foreword:
`This book, written by Himanshu Bhatnagar, provides a comprehensive overview of the ASIC design flow targeted for VDSM technologies using the Synopsis suite of tools. It emphasizes the practical issues faced by the semiconductor design engineer in terms of synthesis and the integration of front-end and back-end tools. Traditional design methodologies are challenged and unique solutions are offered to help define the next generation of ASIC design flows. The author provides numerous practical examples derived from real-world situations that will prove valuable to practicing ASIC design engineers as well as to students of advanced VLSI courses in ASIC design'.
Dr Dwight W. Decker, Chairman and CEO, Conexant Systems, Inc., (Formerly, Rockwell Semiconductor Systems), Newport Beach, CA, USA.

Customer Reviews:

Practical Text.......2002-01-29

As an ASIC designer I found this to be useful when doing synthesis work. If you are experienced in synthesis, synopsys online documentation and personal notes may prove as useful. I simply liked this text. The price is really not that far out of norm for technical books such as this one.

very general; very short; and way over priced.......2001-05-16

This book is very general even to readers who are unfamiliar with the topic. It is a waste of money. It is extremely short, I read the whole book in one day. It has bits and pieces here and there, but no fundamentals. This book is not useful, even to starters.

very general; very short; not worth the money.......2001-05-16

This book is extremely general. Even for readers who do not want to practice synthesis or timing analysis. It gives very few minor examples. It is not worth the money. I finished reading the book in 1 day. The information in this book is so shallow. I wasted my money. If you have access to the synopsys tools, it is much better to read the tools user guide.

Advanced Asic Chip Synthesis: Using Synopsys Design Compiler.......2001-02-17

This book offers nothing extra from Synopsys On-Line Documentation. It is simply over overpriced.

Highly overpriced, bad English, poor typeset.......2001-02-15

I got turned off from this book the moment I opened it, and before I even read a single line. It has huge font size (even larger, instead of smaller, for example scripts) and one-inch margins on top and bottom. (An O'Reilly book has 40% more information on same-sized page, and it's far easier to read.) Every other sentence contains a punctuation error. All this makes it hard to concentrate on the content.

The content itself is good for the absolute beginner, but not much else. The example scripts have no useful comments. Several important concepts (wire-load models among them) are mentioned without explanation. Other concepts (such as false paths) are explained in a misleading way.

The author may be a superb designer, but that does not automatically make him a decent writer.

Book Description

The aim of Surviving the SOC Revolution: A Guide to Platform-Based Design is to provide the engineering community with a thorough understanding of the challenges involved when moving to system-on-a-chip and deliver a step-by-step methodology to get them there.
Design reuse is most effective in reducing the cost and development time when the components to be shared are close to the final implementation. On the other hand, it is not always possible or desirable to share designs at this level, since minimal variations in specification can result in different, albeit similar, implementations. However, moving higher in abstraction can eliminate the differences among designs, so that the higher level of abstraction can be shared and only a minimal amount of work needs to be carried out to achieve final implementation.
The ultimate goal is to create a library of functions and of hardware and software implementations that can be used for all new designs. It is important to have a multilevel library, since it is often the case that the lower levels that are closer to the physical implementation change because of the advances in technology, while the higher levels tend to be stable across product versions.
It is most likely that the preferred approaches to the implementation of complex embedded systems will include the following aspects:

Design costs and time are likely to dominate the decision-making process for systems designers. Therefore, design reuse in all its shapes and forms will be of paramount importance.

Designs have to be captured at the highest level of abstraction to be able to exploit all the degrees of freedom that are available.

Next-generation systems will use a few highly complex (Moore's Law Limited) part-types, but many more energy-power-cost-efficient, medium-complexity (10M-100M) gates in 50nm technology chips, working concurrently to implement solutions to complex sensing, computing, and signaling/actuating problems.

Such chips will most likely be developed as an instance of a particular platform. That is, rather than being assembled from a collection of independently developed blocks of silicon functionality, they will be derived from a specific `family' of rnicro-architectures, possibly oriented toward a particular class of problems, that can be modified (extended or reduced) by the system developer.

These platforms will be highly programmable.

Both system and software reuse impose a design methodology that has to leverage existing implementations available at all levels of abstraction. £/LIST£
This book deals with the basic principles of a design methodology that addresses the concerns expressed above. The platform concept is carried throughout the book as a unifying theme to reuse. This is the first book that deals with the platform-based approach to the design of embedded systems and is a stepping stone for anyone who is interested in the real issues facing the design of complex systems-on-chip.
From the Preface by Alberto Sangiovanni-Vincentelli

Customer Reviews:

Not a comprehensive book for SOC design.......2000-09-01

The book explains the fundamentals for design and methodology of SOCs. It also addresses the design reuse concerns. However, the book does not cover practical examples of SOC design and does not explain the difference between ASICs and SOCs.

Code Optimization Techniques for Embedded Processors - Methods, Algorithms, and Tools

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Code Optimization Techniques for Embedded Processors

Code Optimization Techniques for Embedded Processors - Methods, Algorithms, and Tools
Rainer Leupers
Manufacturer: Springer
ProductGroup: Book
Binding: Hardcover

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ASIN: 0792379896

Book Description

The building blocks of today's embedded systems-on-a-chip are complex IP components and programmable processor cores. This means that more and more system functionality is implemented in software rather than in custom hardware. In turn, this indicates a growing need for high-level language compilers, capable of generating efficient code for embedded processors. However, traditional compiler technology hardly keeps pace with new developments in embedded processor architectures. Many existing compilers for DSPs and multimedia processors therefore produce code of insufficient quality with respect to performance and/or code size, and a large part of software for embedded systems is still being developed in assembly languages. As both embedded software as well as processors architectures are getting more and more complex, assembly programming clearly violates the demands for a short time-to-market and high dependability in embedded system design. The goal of this book is to provide new methods and techniques to software and compiler developers, that help to make the necessary step from assembly programming to the use of compilers also in embedded system design.
Code Optimization Techniques for Embedded Processors discusses the state-of-the-art in the area of compilers for embedded processors. It presents a collection of new code optimization techniques, dedicated to DSP and multimedia processors. These include: compiler support for DSP address generation units, efficient mapping of data flow graphs to irregular architectures, exploitation of SIMD and conditional instructions, as well as function inlining under code size constraints. Comprehensive experimental evaluations are given for real-life processors, that indicate the code quality improvements which can be achieved as compared to earlier techniques. In addition, C compiler frontend issues are discussed from a practical viewpoint.
Code Optimization Techniques for Embedded Processors is intended for researchers and engineers active in software development for embedded systems, and for compiler developers in academia and industry.

Customer Reviews:

Code Optimization Techniques for Embedded Processors.......2002-02-20

hi
Actually what u r following is good...but...once if i am going through the whole think only ..i think i can give the better suggestion about this website...so like to know more about this site...

Integrating Functional and Temporal Domains in Logic Design:: The False Path Problem and Its Implications (The Springer International Series in Engineering and Computer Science)

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Integrating Functional and Temporal Domains in Logic Design:: The False Path Problem and Its Implications (The Springer International Series in Engineering and Computer Science)
Patrick C. McGeer , and Robert K. Brayton
Manufacturer: Springer
ProductGroup: Book
Binding: Hardcover

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ASIN: 0792391632

Algorithms for VLSI Physical Design Automation, Third Edition

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This book will confuse you
Algorithms for Vlsi Physical Design Automation
Algorithms for Vlsi Physical Design Automation
Suitable for CS people

Algorithms for VLSI Physical Design Automation, Third Edition
Naveed A. Sherwani
Manufacturer: Springer
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Binding: Hardcover

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ASIN: 0792383931

Book Description

Algorithms for VLSI Physical Design Automation, Third Edition covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concepts and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level. Algorithms for VLSI Physical Design Automation, Third Edition provides a comprehensive background in the principles and algorithms of VLSI physical design. The goal of this book is to serve as a basis for the development of introductory-level graduate courses in VLSI physical design automation. It provides self-contained material for teaching and learning algorithms of physical design. All algorithms which are considered basic have been included, and are presented in an intuitive manner. Yet, at the same time, enough detail is provided so that readers can actually implement the algorithms given in the text and use them. The first three chapters provide the background material, while the focus of each chapter of the rest of the book is on each phase of the physical design cycle. In addition, newer topics such as physical design automation of FPGAs and MCMs have been included. The basic purpose of the third edition is to investigate the new challenges presented by interconnect and process innovations. In 1995 when the second edition of this book was prepared, a six-layer process and 15 million transistor microprocessors were in advanced stages of design. In 1998, six metal process and 20 million transistor designs are in production. Two new chapters have been added and new material has been included in almost allother chapters. A new chapter on process innovation and its impact on physical design has been added. Another focus of the third edition is to promote use of the Internet as a resource, so wherever possible URLs have been provided for further investigation. Algorithms for VLSI Physical Design Automation, Third Edition is an important core reference work for professionals as well as an advanced level textbook for students.

Customer Reviews:

This book will confuse you.......2004-10-23

This book is good at introducing basic concepts, if this is what
you want to know. But it is really bad to introduce algorithm.
It simply confuse you. Many time I don't know what the author
is talking about and have to find the original paper, which is
much clear.

Algorithms for Vlsi Physical Design Automation.......2002-05-15

I read the Chapter on clock routing and found that the
author did not do a good job on explaining about DME
algorithm. I got more confused after reading it. So,
I went to the library and checked the references
which gave me clear understanding. Usually, a book
shoud give a reader with a very clear example about
the algorithm it presents. It's was not the case for
the DME algorithm.

Algorithms for Vlsi Physical Design Automation.......2002-01-06

I found this book very helpful in gaining a deeper understanding of what the tools I use are doing. Also, the terminology that is used and explained allows me to easier communication with the CAD developers. I found the information relating to clock skew and jitter of particular value to my daily work.

Suitable for CS people.......1999-07-21

Very comprehensive in VLSI physical design automation. People who major in Computer Science and want to study in VLSI is suitable to buy this book. Also people who want to develop EDA tools can buy the book.

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